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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- The philosophy of open ISAs and the standardization efforts led by RISC-V International.
- Core mental model of RISC-V: Load-Store architecture, register files, and byte ordering conventions.
- Comparative analysis with ARM, x86, and POWER architectures: evaluating trade-offs for heterogeneous computing environments.
- Assessment of ecosystem maturity, focusing on key players like SiFive, T-Head, Western Digital, and the expanding open-source silicon community.
- Understanding standardized interfaces, including the RISC-V Privileged ISA and the Machine Software Abstraction Layer (MSBL).
Memory Models and ABI Compliance
- Exploration of the Unprivileged Architecture specification: CSR maps, exception handling mechanisms, and memory hierarchy structures.
- Overview of RV32I and RV64I instruction sets and their role in ensuring cross-platform binary portability through ABI compliance.
- Examination of memory ordering conventions and barrier instructions essential for multiprocessor system synchronization.
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Mastery of base integer instructions (I), Multiply/Divide (M), and Atomic operations (A) extensions.
- Strategies for bitness-aware programming tailored to 32-bit and 64-bit RISC-V targets.
- Implementation of calling conventions and stack frame management techniques for embedded and real-time software systems.
Compiler Toolchain Proficiency
- Utilization of the LLVM-based compiler toolchain, including Clang, LLVM, and Binutils for RISC-V cross-compilation tasks.
- Configuration of linker scripts, memory sections, and layout settings for bare-metal and RTOS environments.
- Leveraging compiler intrinsics, optimizing code through various optimization levels, and applying profiling-driven tuning methods.
- Navigating open-source toolchain development workflows: building, testing, and packaging custom GCC or Clang toolchains.
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Systems programming in Rust for RISC-V: leveraging zero-cost abstractions, unsafe memory management, and bare-metal development techniques.
- Working in No-Std environments: creating custom linkers, developing device drivers, and managing memory-mapped I/O.
- Development of BSPs for Zephyr RTOS and Buildroot tailored to RISC-V targets.
- Peripheral interfacing skills covering GPIO, I2C, SPI, UART, and DMA controller programming.
Power and Performance Optimization
- Techniques for clock gating, power domain management, and optimizing low-power modes.
- Conducting cycle-accurate performance analysis using simulation profilers and hardware performance counters.
- Tuning real-time interrupt latency to meet the stringent requirements of safety-critical applications.
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- Development of bootloader firmware using OpenSBI, which implements the SBI specification.
- Implementing modern firmware boot stacks on RISC-V using UEFI/EDK II.
- Porting Coreboot and U-Boot to support RISC-V-based single-board computers.
Linux Kernel Integration
- Contributing to the mainline RISC-V kernel: managing device tree overlays, CPU topology, and developing drivers for interrupt controllers (AIA).
- Creating vendor BSPs and configuring the kernel for custom SoC platforms.
- Enabling file system support, networking stacks, and containerization capabilities (Docker, Kubernetes) on RISC-V host systems.
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Applying Network-on-Chip (NoC) design methodologies for multi-core RISC-V processors.
- Implementing Axi4/CHI cache coherence protocols and inter-processor communication standards.
- Integrating open-source IP sources such as OpenCores, the ChIPS Framework, and vendor-specific RTL components.
- Designing bus matrices and integrating memory controllers for DDR, SRAM, eMMC, and PCIe interfaces.
FPGA-Based Processor Prototyping
- Synthesizing and implementing RISC-V cores (e.g., BOOM, VexRiscv, PULP) on FPGA platforms.
- Employing SystemVerilog Assertions (SVA) and UVM-based methodologies for functional verification.
- Utilizing formal verification tools and property-based testing to validate RISC-V core functionality.
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Exploiting vector load/store operations, vector-fused multiply-add (VFMA), and matrix computation acceleration.
- Leveraging variable-length vector operations (VL, VLEN) to optimize SIMD execution for specific workloads.
- Utilizing vector mask operations, segment control, and data type flexibility to enhance DSP and ML performance.
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators via custom ISA extensions and CBAR-based operand interfaces.
- Modifying compiler frontends to support the generation and emission of custom instructions.
- Developing hardware-software partitioning strategies for integrating accelerators into production SoCs.
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Architecting Neural Processing Units featuring systolic arrays, tensor cores, and weight compression techniques for on-chip AI acceleration.
- Applying model quantization techniques (INT8, INT4, FP8) suitable for edge deployment on RISC-V hardware.
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets.
Heterogeneous Computing for AI Workloads
- Co-designing RISC-V host CPUs alongside AI accelerator NPUs to enable real-time inference pipelines.
- Optimizing memory subsystems, including HBM/DDR bandwidth management, for ML model weights and activations.
- Managing thermal constraints and power budgets in edge AI inference systems.
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementing Physical Memory Protection (PMP) and securing page table walker mechanisms.
- Deploying Secure Enclave/TEE architectures for RISC-V, including OP-TEE integration and SEV-class trusted execution environments.
- Safeguarding the boot chain through root of trust establishment, secure boot processes, and measured launch attestation.
Cryptographic Acceleration
- Utilizing RISC-V cryptographic extensions (Zk, Zkr, K) for accelerating SHA, AES, RSA, RSA-PSS, and ECC algorithms.
- Integrating Post-Quantum Cryptography (PQC) to prepare next-generation RISC-V processors for future security threats.
- Mitigating side-channel attacks using constant-time programming, masking techniques, and hardware random number generators.
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- Mastering ISA extension design methodology: encoding schemes, encoding tables, ABI impact analysis, and the submission process to RISC-V International.
- Designing custom register files with CBAR (Custom Base Address Registers) for efficient operand dispatch.
- Implementing instruction pipelining, hazard detection logic, and pipeline modifications to support custom extensions.
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions using both directed and constraint-random stimulus generation.
- Establishing regression testing frameworks and coverage-driven verification processes for architectural changes.
- Conducting interoperability testing to ensure custom instructions operate correctly within established ABI constraints.
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for automotive processors based on RISC-V.
- Developing ASIL-Q classifications and safety manuals for RISC-V silicon IP products.
- Implementing deterministic interrupt handling, lockstep core pairs, and robust memory protection for safety-critical systems.
Industrial Real-Time and Edge Computing Applications
- Meeting IEC 61508 SIL compliance requirements and implementing deterministic scheduling on RISC-V multicore platforms.
- Developing Industrial IoT gateways using RISC-V, focusing on connectivity, edge analytics, and OTA firmware update systems.
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: Defining ISA extensions and core configurations for a specific use case.
- RTL implementation in SystemVerilog, accompanied by UVM testbenches and formal verification coverage analysis.
- FPGA prototyping, boot firmware development, and integration of the bare-metal driver stack.
- Customizing the Linux BSP and toolchain for the bespoke RISC-V core.
- Deploying AI workloads through NPU integration, model quantization, and comprehensive performance benchmarking.
- Executing security validation: enforcing PMP, implementing secure boot, and benchmarking cryptographic acceleration.
- Producing technical architecture documentation, conducting IP strategy analysis, and presenting findings to a cross-functional team.
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
